// Cell names have been changed in this file by netl_namemap on Mon Jan  3 04:00:09 UTC 2022
//////////////////////////////////////////////////////////////////////////////
//
//  jtag_ctl.v
//
//  Top-level of JTAG controller which includes generic JTAG FSM as well as
//  implementation-specific registers
//
//  Original Author: Chris Jones
//  Current Owner:   Behram Minwalla
//
//////////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2011 Synopsys, Inc.  All rights reserved.
//
// SYNOPSYS CONFIDENTIAL - This is an unpublished, proprietary work of
// Synopsys, Inc., and is fully protected under copyright and trade secret
// laws.  You may not view, use, disclose, copy, or distribute this file or
// any information contained herein except pursuant to a valid written
// license agreement. It may not be used, reproduced, or disclosed to others
// except in accordance with the terms and conditions of that agreement.
//
//////////////////////////////////////////////////////////////////////////////
//
//    Perforce Information
//    $Author: ameer $
//    $File: //dwh/up16/main/dev/pcs_raw/dig/rtl/jtag_ctl.v $
//    $DateTime: 2014/09/21 23:31:25 $
//    $Revision: #9 $
//
//////////////////////////////////////////////////////////////////////////////

`include "dwc_e12mp_phy_x4_ns_jtag_macros.v"
`include "dwc_e12mp_phy_x4_ns_jtag_id_code.v"

`timescale 1ns/10fs
module dwc_e12mp_phy_x4_ns_jtag_ctl (
// TAP interface
input  wire         jtag_trst_n,
//input  wire         jtag_tck,
input  wire         jtag_tms,
input  wire         jtag_tdi,
output wire         jtag_tdo,
output wire         jtag_tdo_en,

// Scan interface
input  wire         scan_mode,
input  wire         scan_set_rst,

// Generic JTAG register control signals
input  wire         jtag_clk,
input  wire         jtag_clk_n,
//output  wire         jtag_clk,
//output  wire         jtag_clk_n,
output wire         jtag_rst,
output wire         jtag_ser_in,
output wire         jtag_capture,
output wire         jtag_shift,
output wire         jtag_update,

// Individual JTAG registers not contained herein
output wire         jtag_crsel_sel,
input  wire         jtag_crsel_tdo
);

wire [`DWC_E12MP_X4NS_JTAG_DR_IDCODE_LEN-1:0]  idcode;
wire [`DWC_E12MP_X4NS_JTAG_IR_WIDTH-1:0]       jtag_ir;
wire                                 idcode_sel;
wire                                 idcode_tdo;
wire                                 byp_sel;
wire                                 byp_tdo;
wire                                 byp;

reg                                  jtag_mux_tdo;

// MOVED TO PCS_RAW_AON_CMN BLOCK
//
// // Create a positive and negative jtag clocks to deal with falling-edge flops
// //
// assign jtag_clk = jtag_tck;
// //assign jtag_clk_n = ~jtag_tck;
// gen_clk_mux jtag_clk_n_mux(
//   .out (jtag_clk_n),
//   .sel (scan_mode),
//   .d0  (~jtag_tck),
//   .d1  (jtag_tck)
// );

// JTAG FSM - generic JTAG controller
//
dwc_e12mp_phy_x4_ns_jtag_fsm #(.IR_WIDTH(`DWC_E12MP_X4NS_JTAG_IR_WIDTH),
           .IR_IDCODE(`DWC_E12MP_X4NS_JTAG_IR_IDCODE))
fsm (
  .trst_n            (jtag_trst_n),
  .tck               (jtag_clk),
  .tck_n             (jtag_clk_n),
  .tms               (jtag_tms),
  .tdi               (jtag_tdi),
  .tdo               (jtag_tdo),
  .tdo_en            (jtag_tdo_en),
  .jtag_ir           (jtag_ir),
  .jtag_rst          (jtag_rst),
  .jtag_idle         (),
  .jtag_select       (),
  .jtag_capture      (jtag_capture),
  .jtag_shift        (jtag_shift),
  .jtag_update       (jtag_update),
  .jtag_ser_out      (jtag_mux_tdo),
  .scan_mode_i       (scan_mode),
  .scan_set_rst_i    (scan_set_rst)
);

// Serial shift in stream to all JTAG registers from JTAG TDI
//
assign jtag_ser_in = jtag_tdi;

// Final MUX for serial shift out of registers on to JTAG TDO
//
// ASSERT: Add a one-hot assertion to the below selects
//
always @*
  case (1'b1)
    idcode_sel       : jtag_mux_tdo = idcode_tdo;
    jtag_crsel_sel   : jtag_mux_tdo = jtag_crsel_tdo;
    byp_sel          : jtag_mux_tdo = byp_tdo;
    default          : jtag_mux_tdo = 1'bX;
  endcase

// IDCODE register
//
assign idcode_sel = (jtag_ir == `DWC_E12MP_X4NS_JTAG_IR_IDCODE);
dwc_e12mp_phy_x4_ns_jtag_reg #(.WIDTH(`DWC_E12MP_X4NS_JTAG_DR_IDCODE_LEN),
           .RST_VAL(0))
idcode_reg (
  .q            (idcode),
  .serial_out   (idcode_tdo),
  .select       (idcode_sel),
  .capture_val  ({`DWC_E12MP_X4NS_JTAG_DR_IDCODE_VAL_HI, `DWC_E12MP_X4NS_JTAG_DR_IDCODE_VAL_LO}),
  .rst          (jtag_rst),
  .clk          (jtag_clk),
  .capture      (jtag_capture),
  .shift        (jtag_shift),
  .serial_in    (jtag_ser_in)
);

// Select lines for JTAG registers not contained within this module
//
assign jtag_crsel_sel   = (jtag_ir == `DWC_E12MP_X4NS_JTAG_IR_CRSEL);

// BYPASS register - selected when no other register is selected
//
assign byp_sel = (!idcode_sel && !jtag_crsel_sel);

dwc_e12mp_phy_x4_ns_jtag_reg #(.WIDTH(1),
           .RST_VAL(1'b0))
byp_reg (
  .q            (byp),
  .serial_out   (byp_tdo),
  .select       (byp_sel),
  .capture_val  (1'b0),
  .rst          (jtag_rst),
  .clk          (jtag_clk),
  .capture      (jtag_capture),
  .shift        (jtag_shift),
  .serial_in    (jtag_ser_in)
);

endmodule
